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HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM
128-MBit Synchronous DRAM
* High Performance: -7 -7.5 133 7.5 5.4 10 6 -8 125 8 6 10 6 Units MHz ns ns ns ns
* Multiple Burst Read with Single Write Operation * Automatic and Controlled Precharge Command * Data Mask for Read/Write Control (x4, x8) * Data Mask for byte control (x16) * Auto Refresh (CBR) and Self Refresh * Power Down and Clock Suspend Mode * 4096 Refresh Cycles / 64 ms
fCK tCK3 tAC3 tCK2 tAC2
143 7 5.4 7.5 5.4
* Single Pulsed RAS Interface * Fully Synchronous to Positive Clock Edge * 0 to 70 C operating temperature * Four Banks controlled by BA0 & BA1 * Programmable CAS Latency: 2, 3 * Programmable Wrap Sequence: Sequential or Interleave * Programmable Burst Length: 1, 2, 4, 8 and full page
* Random Column Address every CLK (1-N Rule) * Single 3.3 V 0.3 V Power Supply * LVTTL Interface * Plastic Packages: P-TSOPII-54 400mil x 875 mil width (x4, x8, x16) * -7 for PC 133 2-2-2 applications -7.5 for PC 133 3-3-3 applications -8 for PC100 2-2-2 applications
The HYB 39S128400/800/160CT are four bank Synchronous DRAM's organized as 4 banks x 8MBit x4, 4 banks x 4MBit x8 and 4 banks x 2Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using the Infineon advanced 0.17 micron process technology. The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V 0.3 V power supply and are available in TSOPII packages.
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Ordering Information Type HYB 39S128400CT-7 HYB 39S128400CT-7.5 HYB 39S128400CT-8 HYB 39S128800CT-7 HYB 39S128800CT-7.5 HYB 39S128800CT-8 HYB 39S128160CT-7 HYB 39S128160CT-7.5 HYB 39S128160CT-8 HYB 39S128160CTL-8 HYB 39S128160CTL-7.5 Function Code Package Description
PC133-222-520 P-TSOP-54 (400mil) 143MHz 4B x 8M x4 SDRAM PC133-333-520 P-TSOP-54 (400mil) 133 MHz 4B x 8M x4 SDRAM PC100-222-620 P-TSOP-54 (400mil) 100 MHz 4B x 8M x4 SDRAM PC133-222-520 P-TSOP-54 (400mil) 143 MHz 4B x 4M x8 SDRAM PC133-333-520 P-TSOP-54 (400mil) 133 MHz 4B x 4M x8 SDRAM PC100-222-620 P-TSOP-54 (400mil) 100 MHz 4B x 4M x8 SDRAM PC133-222-520 P-TSOP-54 (400mil) 143 MHz 4B x 2M x16 SDRAM PC133-333-520 P-TSOP-54 (400mil) 133 MHz 4B x 2M x16 SDRAM PC100-222-620 P-TSOP-54 (400mil) 100 MHz 4B x 2M x16 SDRAM PC100-222-620 P-TSOP-54 (400mil) 100 MHz 4B x 2M x16 SDRAM
Low Power ("L") version
PC133-333-520 P-TSOP-54 (400mil) 133 MHz 4B x 2M x16 SDRAM
Low Power ("L") version
Pin Definitions and Functions CLK CKE CS RAS CAS WE A0 - A11 BA0, BA1 Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select DQ DQM, LDQM, UDQM Data Input/Output Data Mask Power (+ 3.3 V) Ground Power for DQ's (+ 3.3 V) Ground for DQ's Not connected
VDD VSS VDDQ VSSQ
N.C.
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8 M x 16 16 M x 8 32 M x 4
VDD
DQ0
VDD
DQ0
VDD
N.C.
VDDQ
DQ1 DQ2
VDDQ
N.C. DQ1
VDDQ
N.C. DQ0
VSSQ
DQ3 DQ4
VSSQ
N.C. DQ2
VSSQ
N.C. N.C.
VDDQ
DQ5 DQ6
VDDQ
N.C. DQ3
VDDQ
N.C. DQ1
VSSQ
DQ7
VSSQ
N.C.
VSSQ
N.C.
VDD
LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3
VDD
N.C. WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3
VDD
N.C. WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3
VDD
VDD
VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS
N.C.
VSS
DQ7
VSS
DQ15
VSSQ
N.C. DQ3
VSSQ
N.C. DQ6
VSSQ
DQ14 DQ13
VDDQ
N.C. N.C.
VDDQ
N.C. DQ5
VDDQ
DQ12 DQ11
VSSQ
N.C. DQ2
VSSQ
N.C. DQ4
VSSQ
DQ10 DQ9
VDDQ
N.C.
VDDQ
N.C.
VDDQ
DQ8
VSS
N.C. DQM CLK CKE N.C. A11 A9 A8 A7 A6 A5 A4
VSS
N.C. DQM CLK CKE N.C. A11 A9 A8 A7 A6 A5 A4
VSS
N.C. UDQM CLK CKE N.C. A11 A9 A8 A7 A6 A5 A4
VSS
VSS
VSS
TSOPII-54 (10.16 mm x 22.22 mm, 0.8 mm pitch)
SPP04121
Pin Configuration for x4, x8 & x16 Organized 128M-DRAMs
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Functional Block Diagrams
Column Addresses A0 - A9, A11, AP, BA0, BA1
Row Addresses A0 - A11, BA0, BA1
Column Address Counter
Column Address Buffer
Row Address Buffer
Refresh Counter
Row Decoder
Row Decoder
Row Decoder
Row Decoder
Column Decoder Sense amplifier & I(O) Bus
Column Decoder Sense amplifier & I(O) Bus
Column Decoder Sense amplifier & I(O) Bus
Bank 0 4096 x 2048 x 4 Bit
Bank 1 4096 x 2048 x 4 Bit
Bank 2 4096 x 2048 x 4 Bit
Column Decoder Sense amplifier & I(O) Bus
Memory Array
Memory Array
Memory Array
Memory Array
Bank 3 4096 x 2048 x 4 Bit
Input Buffer
Output Buffer
Control Logic & Timing Generator
DQ0 - DQ3
Block Diagram: 32M x4 SDRAM (12 / 11 / 2 addressing)
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CLK CKE CS RAS CAS WE DQM
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Column Addresses A0 - A9, AP, BA0, BA1
Row Addresses A0 - A11, BA0, BA1
Column Address Counter
Column Address Buffer
Row Address Buffer
Refresh Counter
Row Decoder
Row Decoder
Row Decoder
Row Decoder
Column Decoder Sense amplifier & I(O) Bus
Column Decoder Sense amplifier & I(O) Bus
Column Decoder Sense amplifier & I(O) Bus
Bank 0 4096 x 1024 x 8 Bit
Bank 1 4096 x 1024 x 8 Bit
Bank 2 4096 x 1024 x 8 Bit
Column Decoder Sense amplifier & I(O) Bus
Memory Array
Memory Array
Memory Array
Memory Array
Bank 3 4096 x 1024 x 8 Bit
Input Buffer
Output Buffer
Control Logic & Timing Generator
DQ0 - DQ7
Block Diagram: 16M x8 SDRAM (12 / 10 / 2 addressing)
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CLK CKE CS RAS CAS WE DQM
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HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM
Column Addresses A0 - A8, AP, BA0, BA1
Row Addresses A0 - A11, BA0, BA1
Column Address Counter
Column Address Buffer
Row Address Buffer
Refresh Counter
Row Decoder
Row Decoder
Row Decoder
Row Decoder
Column Decoder Sense amplifier & I(O) Bus
Column Decoder Sense amplifier & I(O) Bus
Column Decoder Sense amplifier & I(O) Bus
Memory Array
Memory Array
Memory Array
Column Decoder Sense amplifier & I(O) Bus
Memory Array
Bank 0 4096 x 512 x 16 Bit
Bank 1 4096 x 512 x 16 Bit
Bank 2 4096 x 512 x 16 Bit
Bank 3 4096 x 512 x 16 Bit
Input Buffer
Output Buffer
Control Logic & Timing Generator
DQ0 - DQ15
Block Diagram: 8M x16 SDRAM (12 / 9 / 2 addressing)
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CLK CKE CS RAS CAS WE DQMU DQML
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Signal Pin Description Pin CLK CKE Type Input Input Signal Polarity Function Pulse Level Positive The system clock input. All of the SDRAM inputs are Edge sampled on the rising edge of the clock. Active High Active Low Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiating either the Power Down mode, Suspend mode, or the Self Refresh mode. CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. During a Bank Activate command cycle, A0 - A11 define the row address (RA0 - RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An define the column address (CA0 - CAn) when sampled at the rising clock edge.CAn depends upon the SDRAM organization: 32M x4 SDRAM CA0 - CA9, CA11 (Page Length = 2048 bits) 16M x8 SDRAM CA0 - CA9 (Page Length = 1024 bits) 8M x16 SDRAM CA0 = CA8 (Page Length = 512 bits) In addition to the column address, A10(= AP) is used to invoke the autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 (= AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged regardless of the state of BA0 and BA1. If A10 is low, then BA0 and BA1 are used to define which bank to precharge. BA0, BA1 Input DQx Level - - Bank Select Inputs. Selects which bank is to be active. Data Input/Output pins operate in the same manner as on conventional DRAMs.
CS
Input
Pulse
RAS CAS WE A0 - A11
Input
Pulse
Active Low -
Input
Level
Input Level Output
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Signal Pin Description (cont'd) Pin DQM LDQM UDQM Type Input Signal Polarity Function Pulse Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. One DQM input is present in x4 and x8 SDRAMs, LDQM and UDQM controls the lower and upper bytes in x16 SDRAMs. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity.
VDD VSS VDDQ VSSQ
Supply - Supply -
- -
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Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands.
Operation
Device State Idle3 Any Any Active 3 Active3 Active 3 Active3 Idle Any Active Any Idle Idle Idle (Self Refr.) Idle Active 4 Any (Power Down) Active
CKE n-1 H H H H H H H H H H H H H L
CKE n X X X X X X X X X X X H L H
DQM
BA0 BA1 V V X V V V V V X X X X X X
AP= A10 V L H L H L H V X X X X X X
Addr A11, A9-0 V X X V V V V V X X X X X X
CS
RAS
CAS
WE
Bank Active Bank Precharge Precharge All Write Write with Autoprecharge Read Read with Autoprecharge Mode Register Set No Operation Burst Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit
X X X X X X X X X X X X X X
L L L L L L L L L L H L L H L H
L L L H H H H L H H X L L X H X H X H X X
H H H L L L L L H H X L L X H X H X H X X
H L L L L H H L H L X H H X X X X X L X X
Power Down Entry (Precharge or active standby) Power Down Exit
H
L
X
X
X
X
L H
L H H
H X X
X L H
X X X
X X X
X X X
L X X
Data Write/Output Enable
Data Write/Output Disable Active
Notes: 1. V = Valid, x = Don't Care, L = Low Level, H = High Level. 2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3. This is the state of the banks designated by BA0, BA1 signals. 4. Power Down Mode can not entry in the burst cycle. When this command is asserted in the burst mode cycle the device is in clock suspend mode.
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Address Inputs for Mode Register Set Operation
BA1 BA0 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus (Ax)
Operation Mode
CAS Latency
BT
Burst Length
Mode Register (Mx)
Operation Mo de BA1 BA0 M11 M10 M9 0 0 0 0 0 0 0 0 0 1 M8 0 0 M7 0 0 Mode Burst Read/ Burst Write Burst Read/ Single Write
B urst Typ e M3 0 1 Type Sequential Interleave
CA S L atency M6 0 0 0 0 1 1 1 1 M5 0 0 1 1 0 0 1 1 M4 0 1 0 1 0 1 0 1 Reserved Latency Reserved Reserved 2 3
B u rst L engt h M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 Full Page
SPD04125_FP
Length Sequential 1 2 4 8 Interleave 1 2 4 8
Reserved
Reserved
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Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VDD and V DDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power on voltage must not exceed VDD + 0.3 V on any of the input pins or VDD supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 s is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. Programming the Mode Register The Mode register designates the operation mode at the read or write cycle. This register is divided into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency Field to set the access time at clock cycle and a Operation mode field to differentiate between normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode. After the initial power up, the mode set operation must be done before any activate command. Any content of the mode register can be altered by re-executing the mode set command. All banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table. Read and Write Operation When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, t RCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 143 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is `2', then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. Full page burst operation is only possible using sequential burst type and page length is a function of the I/O organisation and column addressing. Full page burst operation does not self terminate
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once the burst length has been reached. In other words, unlike burst length of 2, 4, and 8, full page burst continues until it is terminated using another command. Similar to the page mode of conventional DRAM's, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum t RAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycle is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. Once two or more banks are activated, column to column interleave operation can be performed between different pages. Burst Length and Sequence Burst Length 2 4 Starting Address (A2 A1 A0) xx0 xx1 x00 x01 x10 x11 000 001 010 011 100 101 110 111 nnn 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 Sequential Burst Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 Interleave Burst Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
8
Full Page Refresh Mode
Cn, Cn+1, Cn+2....
not supported
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-RAS refresh of conventional DRAMs. All of banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock timing. The mode restores word line after the refresh and no external precharge
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command is necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to any access command. DQM Function DQM has two functions for data I/O read and write operations. During reads, when it turns to "high" at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks).
Suspend Mode During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend Latency tCSL).
Power Down In order to reduce standby power consumption, a power down mode is available. All banks must be precharged and the necessary Precharge delay (tRP) must occur before the SDRAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can't remain in Power Down mode longer than the Refresh period (tREF) of the device. Exit from this mode is performed by taking CKE "high". One clock delay is required for power down mode entry and exit. Auto Precharge Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation a time delay equal to tWR (Write recovery time) after the last data in. Precharge Command There is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as shown in the following list. The precharge command can be imposed one clock before the last data out for CAS latency = 2, two clocks before the last data out for CAS latency = 3 and three clocks before the last data out for CAS latency = 4. Writes require a time delay tWR from the last data out to apply the precharge command.
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Bank Selection by Address Bits A10 0 0 0 0 1 BA0 0 0 1 1 x BA1 0 1 0 1 x Bank 0 Bank 1 Bank 2 Bank 3 all Banks
Burst Termination Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory.
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Electrical Characteristics Absolute Maximum Ratings Operating Temperature Range.......................................................................................0 to + 70 C Storage Temperature Range .................................................................................. - 55 to + 150 C Input/Output Voltage ......................................................................................... - 0.3 to VDD + 0.3 V Power Supply Voltage V DD/V DDQ .............................................................................. - 0.3 to + 4.6 V Power Dissipation ....................................................................................................................... 1 W Data out Current (short circuit) ............................................................................................... 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operation and DC Characteristics
TA = 0 to 70 C; VSS = 0 V; VDD ,VDDQ = 3.3 V 0.3 V
Parameter Input High Voltage Input Low Voltage Output High Voltage (I OUT = - 4.0 mA) Output Low Voltage (IOUT = 4.0 mA) Input Leakage Current, any input (0 V < VIN < VDDQ, all other inputs = 0 V) Output Leakage Current (DQ is disabled, 0 V < V OUT < V DD) Symbol min. Limit Values max. 2.0 - 0.3 2.4 - -5 -5 Unit Notes V V V V
1, 2 1, 2
VIH VIL VOH VOL II(L) IO(L)
VDD + 0.3
0.8 - 0.4 5 5
- - - -
A A
Notes 1.)All voltages are referenced to VSS . 2.)VIH may overshoot to VDD + 2.0 V for pulse width of < 4 ns with 3.3 V. VIL may undershoot to - 2.0 V for pulse width < 4.0 ns with 3.3 V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
Capacitance
TA = 0 to 70 C; VDD = 3.3 V 0.3 V, f = 1 MHz
Parameter Input Capacitance (CLK) Input Capacitance (A0 - A11, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM) Input/Output Capacitance (DQ) Symbol Values min. max. 3.5 3.8 6.0 pF pF pF 2.5 2.5 4.0 Unit
CI1 CI2 CIO
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Operating Currents
TA = 0 to 70 C, VDD = 3.3 V 0.3 V
(Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition Operating current - Symb. -7 -7.5 max. -8 Unit Note
ICC1
170 160 1.5 150 mA mA
3,4
tCK = tCK(MIN.),All banks operated
in random access,all banks operated in ping-pong manner Precharge standby current in Power Down Mode CS = V IH (MIN.), CKE V IL(MAX.) Precharge standby current in Non Power Down Mode CS = V IH (MIN.), CKE V IH(MIN.) No operating current tCK = min., CS = VIH (MIN.), active state (max. 4 banks)
tCK = min
ICC2P
3
tCK = min
ICC2N
45
40
35
mA
3
CKE VIH(MIN.)
ICC3N
50
50 10
45
mA mA
3 3
CKE VIL(MAX.) ICC3P
- Burst Operating Current tCK = min,Read command cycling Auto Refresh Current tCK = min, trc = trcmin. Auto Refresh command cycling Self Refresh Current Self Refresh Mode CKE = 0.2 V, tck=infinity Notes -
ICC4
110 100 230 90 210 mA mA
3, 4 3
ICC5
250
standard version L-version
ICC6
1.5 690
mA
A
5. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7 & -7.5 and at 100 MHz for -8 parts. Input signals are changed once during tCK. 6. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3 and BL = 4 is assumed and the VDDQ current is excluded.
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AC Characteristics
1, 2
TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V, tT = 1 ns
Parameter Symb. -7 min. Clock and Clock Enable Clock Cycle Time CAS Latency = 3 tCK CAS Latency = 2 Clock frequency CAS Latency = 3 tCK CAS Latency = 2 Access Time from Clock CAS Latency = 3 tAC CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Transition Time Setup and Hold Times Input Setup Time Input Hold Time CKE Setup Time CKE Hold Time Mode Register Set-up Time Power Down Mode Entry Time Common Parameters Row to Column Delay Time Row Precharge Time Row Active Time Row Cycle Time Activate(a) to Activate(b) Command Period - 7 7.5 - - - - 2.5 2.5 0.3 - - 143 133 5.4 5.4 - - 1.2 7.5 10 - - - - 2.5 2.5 0.3 - - 133 100 5.4 6 - - 1.2 8 10 - - - - 3 3 0.5 - - 125 100 6 6 - - 10 ns ns - MHz MHz
2, 3, 6
Limit Values -7.5 min. max. min. -8 max. max.
Unit
Note
ns ns ns ns ns - - -
tCH tCL tT
tIS tIH tCKS tCKH tRSC tSB
1.5 0.8 1.5 0.8 2 0
- - - - - 7
1.5 0.8 1.5 0.8 2 0
- - - - - 7.5
2 1 2 1 2 0
- - - - - 8
ns ns ns ns CLK ns
4 4 4 4
- -
tRCD tRP tRAS tRC tRRD
15 15 42 60 14 1
- - 100k - - -
20 20 45 67 15 1
- - 100k - - -
20 20 48 70 16 1
- - 100k - - -
ns ns ns ns ns CLK
5 5 5 5 5
CAS(a) to CAS(b) Command tCCD Period
-
INFINEON Technologies
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9.01
HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM
AC Characteristics (cont'd)1, 2
TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V, tT = 1 ns
Parameter Symb. -7 min. Refresh Cycle Refresh Period (4096 cycles) Self Refresh Exit Time Read Cycle Data Out Hold Time Data Out to Low Impedance Time max. Limit Values -7.5 min. max. min. -8 max. Unit Note
tREF tSREX
- 1
64 -
- 1
64 -
- 1
64 -
ms CLK
-
tOH tLZ
3 0 3 -
- - 7 2
3 0 3 -
- - 7 2
3 0 3 -
- - 8 2
ns ns ns CLK
2, 5, 6
- - -
Data Out to High Impedance tHZ Time DQM Data Out Disable Latency Write Cycle Write Recovery Time DQM Write Mask Latency Notes
tDQZ
tWR tDQW
2 0
- -
2 0
- -
2 0
- -
CLK CLK
7
-
1. For proper power-up see the operation section of this data sheet. 2. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between V IH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in figure below. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8 V and 2.0 V.
INFINEON Technologies
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9.01
HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM
t CH CLOCK t CL t SETUP INPUT t AC t LZ OUTPUT t HZ
SPT03404
2.4 V 0.4 V tT
t HOLD
1.4 V t AC t OH 1.4 V
I/O 50 pF
Measurement conditions for tAC and tOH
3. If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter. 4. If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter. 5. These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing period (counted in fractions as a whole number) 6. Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load, Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load. 7. The write recovery time twr = 2 CLK cycles is a digital interlock on this device. Special devices with twr = 1 CLK for operations at less or equal 83 MHz will be available.
INFINEON Technologies
19
9.01
HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM
Package Outlines
Plastic Package, P-TSOPII-54 (400 mil, 0.8 mm lead pitch) Thin Small Outline Package, SMD
0.10.05
10.05
155
10.160.13 2)
0.8 155
3) 0.35 +0.1 -0.05
0.15 +0.06 -0.03
0.5 0.1 11.76 0.2
26x 0.8 = 20.8
0.1 54x 0.2 M 54x
54
28
6 max
1 2.5 max 22.220.13 1) Index Marking
1) 2)
27
GPX09039
Does not include plastic or metal protrusion of 0.15 max per side Does not include plastic protrusion of 0.25 max per side 3) Does not include dambar protrusion of 0.13 max per side
INFINEON Technologies
20
9.01
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM Timing Diagrams
1. Bank Activate Command Cycle 2. Burst Read Operation 3. Read Interrupted by a Read 4. Read to Write Interval 4.1 Read to Write Interval 4.2 Minimum Read to Write Interval 4.3 Non-Minimum Read to Write Interval 5. Burst Write Operation 6. Write and Read Interrupt 6.1 Write Interrupted by a Write 6.2 Write Interrupted by Read 7. Burst Write & Read with Auto-Precharge 7.1 Burst Write with Auto-Precharge 7.2 Burst Read with Auto-Precharge 8. AC- Parameters 8.1 AC Parameters for a Write Timing 8.2 AC Parameters for a Read Timing 9. Mode Register Set 10. Power on Sequence and Auto Refresh (CBR) 11. Clock Suspension (using CKE) 11. 1 Clock Suspension During Burst Read CAS Latency = 2 11. 2 Clock Suspension During Burst Read CAS Latency = 3 11. 3 Clock Suspension During Burst Write CAS Latency = 2 11. 4 Clock Suspension During Burst Write CAS Latency = 3 12. Power Down Mode and Clock Suspend 13. Self Refresh ( Entry and Exit ) 14. Auto Refresh ( CBR ) 15. Random Column Read ( Page within same Bank 15.1 CAS Latency = 2 15.2 CAS Latency = 3 16. Random Column Write ( Page within same Bank) 16.1 CAS Latency = 2 16.2 CAS Latency = 3 17. Random Row Read ( Interleaving Banks) with Precharge 17.1 CAS Latency = 2 17.2 CAS Latency = 3 18. Random Row Write ( Interleaving Banks) with Precharge 18.1 CAS Latency = 2 18.2 CAS Latency = 3 19. Precharge Termination of a Burst 20. Full Page Burst Operation 20.1 Full Page Burst Read, CAS Latency = 2 18.2 Full Page Burst Write, CAS Latency = 3 page 22 page 23 page 24 page 24 page 24 page 25 page 25 page 26 page 27 page 27 page 27 page 28 page 28 page 28 page 29 page 29 page 30 page 31 page 32 page 33 page 33 page 34 page 35 page 36 page 37 page 38 page 39 page 40 page 40 page 41 page 42 page 42 page 43 page 44 page 44 page 45 page 46 page 46 page 47 page 48 page 49 page 49 page 50
INFINEON Technologies
22
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 1. Bank Activate Command Cycle
(CAS latency = 3)
T0 CLK T1 T T T T T
Address
Bank B Row Addr.
Bank B Col. Addr.
Bank A Row Addr.
Bank B Row Addr.
t RCD Command
Bank B Activate
t RRD NOP
Write B with Auto Precharge
NOP
Bank A Activate
NOP
Bank B Activate
t RC "H" or "L"
SPT03784
2. Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Read A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
SPT03712
INFINEON Technologies
23
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 3. Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Read A
Read B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
SPT03713
4. Read to Write Interval 4.1 Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0 CLK Minimum delay between the Read and Write Commands = 4 + 1 = 5 cycles DQMx t DQZ Command NOP Read A NOP NOP NOP NOP Write B NOP NOP Write latency t DQW of DQMx T1 T2 T3 T4 T5 T6 T7 T8
DQ's
DOUT A0
DIN B0
DIN B1
DIN B2
Must be Hi-Z before the Write Command "H" or "L"
SPT03787
INFINEON Technologies
24
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 4 2. Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
DQM t DQZ
t DQW
1 Clk Interval Command NOP NOP
Bank A Activate
NOP
Read A
Write A
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's
Must be Hi-Z before the Write Command DIN A0 DIN A1 DIN A2 DIN A3
"H" or "L"
SPT03939
4. 3. Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
DQM t DQZ Command NOP Read A NOP NOP Read A NOP
t DQW
Write B
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's "H" or "L"
Must be Hi-Z before the Write Command DOUT A0 DOUT A1 DIN B0 DIN B1 DIN B2
DOUT A0
DIN B0
DIN B1
DIN B2
SPT03940
INFINEON Technologies
25
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 5. Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
NOP
Write A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQ's
DIN A0
DIN A1
DIN A2
DIN A3
don't care
The first data element and the Write are registered on the same clock edge.
Extra data is ignored after termination of a Burst.
SPT03790
INFINEON Technologies
26
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 6. Write and Read Interrupt
6.1 Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK
1 Clk Interval
T1
T2
T3
T4
T5
T6
T7
T8
Command
NOP
Write A
Write B
NOP
NOP
NOP
NOP
NOP
NOP
1 Clk Interval DQ's DIN A0 DIN B0 DIN B1 DIN B2 DIN B3
SPT03791
6.2 Write Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
NOP
Write A
Read B
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's
DIN A0
don't care
DOUT B0 DOUT B1 DOUT B2 DOUT B3
DIN A0
don't care
don't care
DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from the DQ's at least one clock cycle before the Read data appears on the outputs to avoid data contention.
SPT03719
Input data for the Write is ignored.
INFINEON Technologies
27
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 7. Burst Write and Read with Auto Precharge 7.1 Burst Write with Auto-Precharge
(Burst Length = 2, CAS latency = 2, 3 )
T0 CLK
CAS Latency = 2:
T1
T2
T3
T4
T5
T6
T7
T8
Command
Bank A Active
NOP
Write A
Auto Precharge
NOP
NOP t WR
NOP
NOP t RP
Activate
NOP
DQ's
CAS Latency = 3:
DIN A0
DIN A1
*
NOP t WR
Command
Bank A Active
NOP
NOP
Write A
Auto Precharge
NOP
NOP
NOP t RP
NOP
Activate
DQ's
DIN A0
DIN A1
* *
Begin Auto Precharge
Bank can be reactivated after trp
SPT03909 2
7.2 Burst Read with Auto-Precharge
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Read A with AP
NOP
NOP
NOP
NOP
NOP
NOP t RP
NOP
NOP
CAS latency = 2 DQ's CAS latency = 3 DQ's
*
DOUT A0 DOUT A1 DOUT A2 DOUT A3
*
DOUT A0 DOUT A1 DOUT A2
t RP
DOUT A3
* Begin Auto Precharge
Bank can be reactivated after trp
SPT03721_2
INFINEON Technologies
28
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 8. AC Parameters 8.1 AC Parameters for a Write Timing
Burst Length = 4, CAS Latency = 2 T0 CLK t CH t CL t CK2 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE t CKS t CS t CH Begin Auto Precharge Bank A Begin Auto Precharge Bank B t CKH
CS
RAS
CAS
WE
BS tAH AP t AS Addr.
RAx CAx RBx CBx RAy RAy RAz RBy RAx RBx RAy RAz RBy
DQM t RCD t RC Hi-Z DQ Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 t WR t RP t DS t DH t WR t RP t RRD
Ay0 Ay1 Ay2 Ay3
Activate Command Bank A
Activate Command Bank B Write with Auto Precharge Command Bank B
Activate Write Command Command Bank A Bank A
Precharge Activate Activate Command Command Command Bank A Bank A Bank B
Write with Auto Precharge Command Bank A
SPT03910_2
INFINEON Technologies
29
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 8.2 AC Parameters for a Read Timing
Burst Length = 2, CAS Latency = 2 T0 CLK t CH t CL CKE t CKS t CH CS RAS CAS WE BS t AH AP t AS Addr. RAx CAx t RRD t RAS DQM tAC2 t LZ t RCD DQ Hi-Z t OH t AC2 t HZ Ax1 Bx0 Bx1 t RC RBx RBx RAy RAx RBx RAy t CS t CK2 t CKH Begin Auto Precharge Bank B T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
t HZ
t RP
Ax0
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read with Auto Precharge Command Bank B
Precharge Command Bank A
Activate Command Bank A
SPT03911_2
INFINEON Technologies
30
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 9. Mode Register Set
CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t RSC
CS RAS CAS WE BS AP
Address Key
Addr.
Precharge Command All Banks
Any Command
Mode Register Set Command
SPT03912_2
INFINEON Technologies
31
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 10. Power on Sequence and Auto Refresh (CBR)
T0
~ ~
T1
T2
T3
T4
T5
T6
T7
T8
~ ~
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
~ ~
CKE
High Level is required
~ ~
~ ~
Minimum of 8 Refresh Cycles are required
~ ~
2 Clock min.
CS RAS CAS WE BS AP
~ ~ ~ ~ ~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~
~ ~
~~ ~~
~~ ~~
~~ ~~
~~ ~~
Address Key
~ ~ ~~ ~~ ~~ ~~
Addr. DQM
t RP DQ
~ ~ ~ ~
~ ~
t RC
Hi-Z
Precharge Command All Banks Inputs must be stable for 200 s 1st Auto Refresh Command
8th Auto Refresh Command
Mode Register Set Command
Any Command
SPT03913
INFINEON Technologies
32
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 11. Clock Suspension ( Using CKE) 11.1 Clock Suspension During Burst Read CAS Latency = 2
Burst Length = 4, CAS Latency = 2 T0 CLK t CK2 CKE CS RAS CAS WE BS AP Addr. DQM t CSL t CSL DQ Hi-Z Ax0 Ax1 Ax2 t CSL Ax3 t HZ
RAx RAx CAx
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Activate Read Command Command Bank A Bank A
Clock Suspend 1 Cycle
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
SPT03914
INFINEON Technologies
33
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 11.2 Clock Suspension During Burst Read CAS Latency = 3
Burst Length = 4, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BS AP Addr. DQM
RAx RAx CAx
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CSL
t CSL
t CSL t HZ
DQ
Hi-Z
Ax0
Ax1
Ax2
Ax3
Activate Command Bank A
Read Command Bank A
Clock Suspend 1 Cycle
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
SPT03915
INFINEON Technologies
34
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 11.3 Clock Suspension During Burst Write CAS Latency = 2
Burst Length = 4, CAS Latency = 2 T0 CLK t CK2 CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3
RAx RAx CAx
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Activate Command Bank A
Clock Suspend 1 Cycle Write Command Bank A
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
SPT03916
INFINEON Technologies
35
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 11.4 Clock Suspension During Burst Write CAS Latency = 3
Burst Length = 4, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BA A8/AP Addr. DQMx DQ Hi-Z DAx0 DAx1 DAx2 DAx3
RAx RAx CAx
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Activate Command Bank A
Clock Suspend 1 Cycle Write Command Bank A
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
SPT03917
INFINEON Technologies
36
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 12. Power Down Mode and Clock Suspend
Burst Length = 4, CAS Latency = 2 T0 CLK t CK2 CKE CS RAS CAS WE BS AP Addr. DQM t HZ DQ Hi-Z Ax0 Ax1 Ax2 Ax3
RAx RAx CAx
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CKS
t CKS
Activate Command Bank A
Active Standby
Read Command Bank A
Clock Mask Start
Clock Mask End
Precharge Command Bank A
Precharge Standby
Any Command
Clock Suspend Mode Entry
Clock Suspend Mode Exit
Power Down Mode Entry
Power Down Mode Exit
SPT03918
INFINEON Technologies
37
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 13. Self Refresh (Entry and Exit)
T0 CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
~ ~ ~ ~
CKE
~ ~
t CKS
t CKS
~ ~
CS
~ ~ ~ ~
RAS
~ ~ ~ ~
CAS
~ ~ ~ ~
WE
~ ~ ~ ~
BS
~~ ~~
AP
~ ~ ~ ~
Addr.
~ ~
t SREX t RC*)
DQM Hi-Z DQ
~ ~ ~ ~
All Banks must be idle
Self Refresh Entry
Begin Self Refresh Exit Command Self Refresh Exit Command issued Self Refresh Exit
Any Command
*) minimum RAS cycle
time depends on CAS Latency and trc
SPT03919-2
INFINEON Technologies
38
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 14. Auto Refresh (CBR)
Burst Length = 4, CAS Latency = 2 T0 CLK t CK2 CKE T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CS
RAS
CAS
WE
BS
RAx
AP
Addr. t RC DQM Hi-Z DQ t RP (Minimum Interval) t RC
RAx
CAx
Ax0 Ax1 Ax2 Ax3
Precharge Auto Refresh Command Command All Banks
Auto Refresh Command
Activate Read Command Command Bank A Bank A
SPT03920_2
INFINEON Technologies
39
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 15. Random Column Read (Page within same Bank) 15.1 CAS Latency = 2
Burst Length = 4, CAS Latency = 2 T0 CLK t CK2 CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3
RAw RAw CAw CAx CAy RAz RAz CAz
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
SPT03921
INFINEON Technologies
40
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 15.2 CAS Latency = 3
Burst Length = 4, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
RAw RAw CAw CAx CAy RAz RAz CAz
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A SPT03922
INFINEON Technologies
41
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 16. Random Column write (Page within same Bank) 16.1 CAS Latency = 2
Burst Length = 4, CAS Latency = 2 T0 CLK t CK2 CKE T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CS
RAS
CAS
WE
BS
AP
RBw
RBz
Addr.
RBw
CBw
CBx
CBy
RBz
CBz
DQM Hi Z DQ
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 DBz3
Activate Write Command Command Bank B Bank B
Write Write Command Command Bank B Bank B
Precharge Activate Read Command Command Command Bank B Bank B Bank B
SPT03923_2
INFINEON Technologies
42
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 16.2. CAS Latency = 3
Burst Length = 4, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1
RBz RBz CBz CBx CBy RBz RBz CBz
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Activate Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B SPT03924
INFINEON Technologies
43
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 17. Random Row Read (Interleaving Banks) with Precharge 17.1 CAS Latency = 2
Burst Length = 8, CAS Latency = 2 T0 CLK t CK2 CKE High T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CS
RAS
CAS
WE
BS
AP
RBx
RAx
RBy
Addr.
RBx
CBx
RAx
CAx
RBy
CBy
t RCD DQM t AC2 Hi-Z DQ
t RP
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7
By0 By1
Activate Read Command Command Bank B Bank B
Activate Command Bank A
Precharge Activate Command Command Bank B Bank B Read Command Bank A
Read Command Bank B
SPT03925_2
INFINEON Technologies
44
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 17.2 CAS Latency = 3
Burst Length = 8, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BS AP Addr.
RBx RBx CBx RAx RAx CAx RBy RBy CBy
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
High
t RCD DQM DQ Hi-Z
t AC3
t RP
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Read Command Bank A
Precharge Command Bank B
Activate Command Bank B
Read Command Bank B
Precharge Command Bank A
SPT03926
INFINEON Technologies
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HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 18. Random Row Write (Interleaving Banks) with Precharge 18.1 CAS Latency = 2
Burst Length = 8, CAS Latency = 2 T0 CLK t CK2 CKE High T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CS
RAS
CAS
WE
BS
AP Addr.
RAx
RBx
RAy
RAx
CAx
RBx
CBx
RAy
CAy
t RCD DQM Hi-Z DQ
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7
t WR
t RP
t WR
DBx0
DBx1 DBx2 DBx3
DBx4
DBx5 DBx6
DBx7 DAy0
DAy1 DAy2
DAy3
DAy4
Activate Write Command Command Bank A Bank A
Activate Write Command Command Bank B Bank B Precharge Command Bank A
Activate Command Bank A
Precharge Command Bank B Write Command Bank A
SPT03927_2
INFINEON Technologies
46
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 18.2 CAS Latency = 3
Burst Length = 8, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx RBx RBx CBx RAy RAy CAy
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
High
t RCD DQM DQ Hi-Z
t WR
t RP
t WR
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B
Precharge Command Bank A
Activate Command Bank A
Write Command Bank A
Precharge Command Bank B
SPT03928
INFINEON Technologies
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HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 19. Precharge termination of a Burst 19.1 CAS Latency = 2
Burst Length = 8 or Full Page, CAS Latency = 2 T0 CLK t CK2 CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx RAy RAy CAy RAz RAz CAz
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
High
t RP DQM
t RP
t RP
DQ
Hi Z
DAx0 DAx1 DAx2 DAx3
Ay0 Ay1 Ay2
Az0 Az1 Az2
Activate Command Bank A
Write Command Bank A Precharge Termination of a Write Burst. Write Data is masked.
Precharge Command Bank A Activate Command Bank A
Read Command Bank A
Precharge Command Bank A Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Precharge Termination of a Read Burst.
SPT03933
INFINEON Technologies
48
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 20. Full Page Burst Operation 20.1 Full Page Burst Read, CAS Latency = 2
Burst Length = Full Page, CAS Latency = 2 T0 CLK t CK2 CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx RBx RBx
~ ~ ~~ ~~ ~ ~
T1
T2
T3
T4
T5
T6
~ ~ ~ ~
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
High
~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~
~ ~
RBy CBx RBy
t RP
~~ ~~
DQM DQ Hi-Z
~ ~
Ax Ax +1 Ax + 2 Ax - 2
Ax -1
Ax
Ax+1 Bx
Bx+1 Bx+2 Bx + 3 Bx+ 4 Bx+ 5 Bx + 6
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval.
Burst Stop Precharge Command Command Bank B Activate Command Bank B
SPT03929
Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
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HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM 20. Full Page Burst Operation 20.2 Full Page Burst Write, CAS Latency = 3
Burst Length = Full Page, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx RBx RBx
~ ~ ~~ ~~ ~ ~
T1
T2
T3
T4
T5
T6
T7
T8
~ ~ ~ ~
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
High
~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~
~ ~
RBy CBx RBy
t RRD
~~ ~~
DQM DQ Hi-Z Ax
~ ~
Ax +1 Ax+ 2 Ax - 2
Ax -1
Ax
Ax +1 Bx
Bx +1 Bx +2 Bx + 3 Bx+ 4 Bx + 5
Activate Command Bank A Read Command Bank A
Activate Command Bank B
Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval.
Burst Stop Precharge Command Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
Activate Command Bank B
SPT03930
INFINEON Technologies
50
HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM
TABLE OF CONTENTS
128-MBit Synchronous DRAM Ordering Information Pin Definitions and Functions Pin Configuration for x4, x8 & x16 Organized 128M-DRAMs Functional Block Diagrams Block Diagram: 32M x4 SDRAM (12 / 11 / 2 addressing Block Diagram: 16M x8 SDRAM (12 / 10 / 2 addressing) Block Diagram: 8M x16 SDRAM (12 / 9 / 2 addressing) Signal Pin Description Operation Definition Address Inputs for Mode Register Set Operation Power On and Initialization Programming the Mode Register Read and Write Operation Refresh Mode Burst Length and Sequence DQM Function Power Down Auto Precharge Precharge Command Burst Termination. Bank Selection by Address Bits Electrical Characteristics Absolute Maximum Ratings Recommended Operation and DC Characteristics Capacitance Operating Currents AC Characteristics Package Outlines. Table of Content. Timing DIagrams.
page 1 page 2 page 2 page 3 page 4 page 4 page 5 page 6 page 7 page 9 page 10 page 11 page 11 page 11 page 12 page 13 page 13 page 13 page 13 page 13 page 14 page 14 page 15 page 15 page 15 page 15 page 16 page 17 page 20 page 21 page 22
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HYB39S128400/800/160CT(L) 128-MBit Synchronous DRAM Attention please !
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. This infomation describes the type of components and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact INFINEON Technologies Offices in Munich or the INFINEON Technologies Sales Offices and Representatives worldwide. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest INFINEON Technologies office or representative.
Packing Please use the recycling operators known to you. We can help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Ciritcal components1 of INFINEON Technologies, may only be used in lifesupport devices or systems2 with the express written approval of INFINEON Technologies. 1. A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect the safety or effectiveness of that device or system. 2. Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
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